This application claims a foreign priority based on German patent application no. 101 02 166.6, filed Jan. 18, 2001 and the contents of that application are incorporated herein by reference.
The invention concerns a device for converting a digital input signal string with an input sampling rate into a digital output signal string with an output sampling rate that is different from the input sampling rate. Such a device is generally called a resampler. The invention also relates to a corresponding method.
Such a resampler is known from European patent document EP 0 665 546 A2, for example. In a resampler, the relationship between the input sampling rate and the output sampling rate must first be determined. In the aforementioned document, this is accomplished through a gate time measurement. The sampled values are interpolated at the output sample times specified by the output sampling rate in an interpolator. In this process, the interpolator is controlled by a detected sampling rate ratio. Since the determination of the sampling rate ratio is subject to measuring inaccuracy, buffering takes place in a buffer store, for example a FIFO, located at the output of the interpolator in the case of down-sampling and at the input of the interpolator in the case of up-sampling. In this regard, the integral behavior of the FIFO memory is exploited. EP 0 665 546 A1 proposes regulating the sampling rate ratio that controls the interpolator as a function of a fill level of the buffer store.
The regulation of the sampling rate ratio as a function of the fill level of the buffer store proposed in EP 0 665 546 A2 has the disadvantage that when the fill level of the buffer store memory changes, the group propagation-time delay of the digital signal through the resampler changes. In applications such as mobile radio telephony, relatively large changes in buffer store fill level (e.g. +/xe2x88x921), which is to say a change by one storage unit, are not tolerable since they lead to variations in propagation-time delay of the signal through the resampler. With the buffer store fill level controller proposed in EP 0 665 546 A1, deviations in a clock rate ratio are detected relatively late, after a relatively large detuning of the ratio has already taken place. This leads to larger interpolation errors due to incorrect sampling times.
Consequently, an object of the invention is to provide a device (resampler) and a method (resampling method) for converting a digital input signal string with an input sampling rate into a digital output signal string with an output sampling rate, which device and/or method functions with high precision.
According to principles of this invention, this object is attained with regard to the device through the features of claim 1, and with regard to the method through the features of claim 9. The dependent claims contain advantageous refinements of the device and/or the method.
The invention is based on the realization that precision in controlling the interpolator and/or in determining the sampling times of the output signal string can be significantly improved if the regulation is not performed solely on the basis of an estimate of the sampling rate ratio between the input sampling rate and the output sampling rate, but also simultaneously on the basis of an estimate of the phase angle. As a result of an inventive phase-coherent regulation, a deviation in the sampling rate ratio is detected before the deviation becomes large enough to lead to a rise or fall in the storage level in the buffer store (FIFO). A great change in the group propagation-time delay through the resampler associated with the change in storage level is thus avoided, and the interpolation precision of the interpolator is improved.